View DM8108_4583574.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

DM8108 8 port 10/100m fast ethernet switching controller preliminary 1 version: DM8108-ds-p02 november 25, 1999 general description the DM8108 is an 8 port 10/100mbit/s nonblocking ethernet switch with on-chip address-lookup engine. the DM8108 provides a low-cost, high-performance switch solution with phys and single sgram. the DM8108 provides eight 10/100mbit/s fast ethernet interface. in half-duplex mode, all ports support back- pressure capab ility to r educe the risk of data loss for a long burst of activity. in the full-duplex mode of operation, the device uses ieee s td. 802.3 frame-based pause protocol for flow control. with full-duplex capab ility, port 0 ? 7 s upport 1.6gbit/s aggregate bandw idth connections. the DM8108 also supports port trunking/load balancing on the 10/100mbit ports. this can be used to group ports on i nter- switch links to increase the effective bandwidth betw een the systems. the internal address-lookup engine supports up to 16.25k unicast and unlimi ted m ulticast and broadcast addresses. this engine performs destination and source addre sses book-keeping and comparison which also forwards unknown destination address packets to all ports. the DM8108 is fabricated with a . 35um technology. working at 3.3v, the i nputs are 5v tolerant and the out puts are capable of directly d riving at ttl levels. block diagram expansion address l earning mem c ontroller led control u nit switching engine control & status
DM8108 8 port 10/100m fast ethernet switching controller 2 preliminary version: DM8108-ds-p02 november 25, 1999 features low cost fast ethernet switching controller. provide packet switching functions between eight 10/100mbps, auto-negotiated on-chip fast ethernet ports and a proprietary full- duplex expansion port. cascade max. 8 DM8108s without extra glue logic for 64-port configuration. incorporates three 802.3 compliant 10/100mbps media access controllers direct interface to mii (media independent interface) half/full duplex support for individual port (up- to 200mbps/port) ieee 802.3 100base-tx, t4.fx compatible auto-negotiation supported through serial mii interface high-performance distributed switching engine performs packet forwarding and filtering at full wire-speed 148,800 packe ts/sec. on each ethernet port direct support for packet buffering glue-less interface with 1 or 2 mbytes of sdram (sgram) 32 bit memory bus configuration 66 mhz ? 90mhz memory bus speed up-to 1.1k buffers, 1536-byte each, allocated to receive ports support store and forward switching approach low last-bit to first-bit out delay allow mixed speed ethernet packet switching allow conversion between different protocols flow control support partitioning function support back-pressure while lack of internal resources support 802.3x pause function in full duplex mode support up to 4-port trunking for 800mbps bandwidth advanced address learning and searching self learning mechanism cache 128 address entries internally record up-to 16k uni-cast mac addresses and unlimited multicast and broadcast addresses automatic aging scheme broadcast filtering rate control expansion bus up-to 8 sw devices can be casc aded via expansion bus without extra logic full duplex mode transfer less bus overhead automatic flow control complete status report to a simple led interface suitable for low cost switch market to replace hub 0.35 m process, 3.3v with 5v toler ant i/o 208-pin pqfp package
DM8108 8 port 10/100m fast ethernet switching controller preliminary 3 version: DM8108-ds-p02 november 25, 1999 application example: low cost 8 to 64 ports 10/100 mbps auto-sensing switch 8 8 8 10/100 basetx cascaded up-to 64 10/ 100mbps fast ethernet ports application example: low cost auto-sensing switching hub imp lementation mii mii #1 hub module #4 hub module 10/100 basetx DM8108 mem phy DM8108 phy DM8108 phy mem mem DM8108 mem phy with repeater phy with repeater phy with r epeater phy with r epeater
DM8108 8 port 10/100m fast ethernet switching controller 4 preliminary version: DM8108-ds-p02 november 25, 1999 high density mixed swit ching and hub ports with 8 co llision do mains
DM8108 8 port 10/100m fast ethernet switching controller preliminary 5 version: DM8108-ds-p02 november 25, 1999 pin configuration DM8108 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 52 51 50 49 53 55 54 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 109 108 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 vss ledclk ledstb ledd rst# testen vss rxer0 rxdv0 col0 crs0 rxclk0 rxd0[0] rxd0[1] rxd0[2] rxd0[3] txclk0 txen0 txd0[0] txd0[1] txd0[2] txd0[3] vdd rxer1 rxdv1 col1 crs1 rxclk1 rxd1[0] rxd1[1] rxd1[2] rxd1[3] txclk1 txen1 txd1[0] txd1[1] txd1[2] txd1[3] vss rxer2 rxdv2 col2 crs2 rxclk2 rxd2[0] rxd2[1] rxd2[2] rxd2[3] txclk2 txen2 txd2[0] txd2[1] vdd rxer3 rxdv3 txd2[2] txd2[3] col3 rxclk3 rxd3[0] crs3 rxd3[1] rxd8[2] rxd8[1] rxd8[0] rxd8[3] rxclk8 vss txd8[3] rxer5 sba sddqm# txd8[2] txd8[1] txd8[0] vdd txclk8 vss dma0 dma1 dma8 dma3 dma4 vss dma5 dma6 dma7 vdd txd4[3] vdd txclk3 txen3 txd3[0] txd3[3] vss miiclk miid vss rxer4 rxdv4 col4 crs4 txd3[2] dma2 dma9 sdcs# ras# sclk vss dmd0 col5 crs5 rxclk5 rxd5[0] rxd5[2] rxd5[3] rxd5[1] txclk5 txen5 txd5[0] txd5[1] txd5[2] txclk6 rxd6[3] txen6 txd6[0] dmd30 dmd29 dmd31 vss dmd9 dmd11 dmd10 dmd12 dmd4 dmd5 dmd3 dmd2 crs7 col7 rxdv7 rxer7 dmd22 dmd23 vss dmd24 dmd1 dmd6 dmd7 vss dwe# vss dmd15 vdd dmd16 dmd18 dmd19 dmd20 txd7[2] dmd8 dmd17 dmd14 dmd21 dmd25 dmd26 dmd27 dmd28 dmd13 txd7[3] txd7[0] txen7 txclk7 rxd7[2] rxd7[1] rxd7[0] rxd7[3] txd6[3] txd6[2] rxd6[0] rxclk6 crs6 rxdv6 rxer6 vss rxd6[2] rxdv5 txd6[1] rxd6[1] col6 vss rxclk4 txen4 rxd4[2] rxd4[1] txd4[0] txclk4 rxd4[0] txd4[1] rxd4[3] txd4[2] vdd rxclk7 txd5[3] rxd3[3] rxd3[2] txd7[1] cas# txd3[1]
DM8108 8 port 10/100m fast ethernet switching controller 6 preliminary version: DM8108-ds-p02 november 25, 1999 pin description pin assignment # name # name # name # name # name 1 vss 43 crs2 85 txen4 127 rxclk7 169 md(4) 2 ledclk 44 rxclk2 86 txd4(0) 128 rxd7(0) 170 md(3) 3 ledstb 45 rxd2(0) 87 txd4(1) 129 rxd7(1) 171 md(2) 4 ledd 46 rxd2(1) 88 txd4(2) 130 rxd7(2) 172 md(1) 5 rst* 47 rxd2(2) 89 txd4(3) 131 rxd7(3) 173 md(0) 6 testen* 48 rxd2(3) 90 vdd 132 txclk7 174 vss 7 vss 49 txclk2 91 rxer5 133 txen7 175 sclk 8 rxer0 50 txen2 92 rxdv5 134 txd7(0) 176 vss 9 rxdv0 51 txd2(0) 93 col5 135 txd7(1) 177 sras* 10 col0 52 txd2(1) 94 crs5 136 txd7(2) 178 sdcas* 11 crs0 53 txd2(2) 95 rxclk5 137 txd7(3) 179 sdcs* 12 rxclk0 54 txd2(3) 96 rxd5(0) 138 vss 180 sdwe* 13 rxd0(0) 55 vdd 97 rxd5(1) 139 md(31) 181 vss 14 rxd0(1) 56 rxer3 98 rxd5(2) 140 md(30) 182 sdqm* 15 rxd0(2) 57 rxdv3 99 rxd5(3) 141 md(29) 183 ma(10) ? sba 16 rxd0(3) 58 col3 100 txclk5 142 md(28) 184 ma(9) 17 txclk0 59 crs3 101 txen5 143 md(27) 185 vdd 18 txen0 60 rxclk3 102 txd5(0) 144 md(26) 186 ma(8) 19 txd0(0) 61 rxd3(0) 103 txd5(1) 145 md(25) 187 ma(7) 20 txd0(1) 62 rxd3(1) 104 txd5(2) 146 md(24) 188 ma(6) 21 txd0(2) 63 rxd3(2) 105 txd5(3) 147 vss 189 ma(5) 22 txd0(3) 64 rxd3(3) 106 vss 148 md(23) 190 vss 23 vdd 65 txclk3 107 rxer6 149 md(22) 191 ma(4) 24 rxer1 66 txen3 108 rxdv6 150 md(21) 192 ma(3) 25 rxdv1 67 txd3(0) 109 col6 151 md(20) 193 ma(2) 26 col1 68 txd3(1) 110 crs6 152 md(19) 194 ma(1) 27 crs1 69 txd3(2) 111 rxclk6 153 md(18) 195 ma(0) 28 rxclk1 70 txd3(3) 112 rxd6(0) 154 md(17) 196 vss 29 rxd1(0) 71 vss 113 rxd6(1) 155 md(16) 197 txenclk 30 rxd1(1) 72 mdclk 114 rxd6(2) 156 vdd 198 vdd 31 rxd1(2) 73 mdio 115 rxd6(3) 157 md(15) 199 txd8(0) 32 rxd1(3) 74 vss 116 txclk6 158 md(14) 200 txd8(1) 33 txclk1 75 rxer4 117 txen6 159 md(13) 201 txd8(2) 34 txen1 76 rxdv4 118 txd6(0) 160 md(12) 202 txd8(3) 35 txd1(0) 77 col4 119 txd6(1) 161 md(11) 203 vss 36 txd1(1) 78 crs4 120 txd6(2) 162 md(10) 204 rxdvclk 37 txd1(2) 79 rxclk4 121 txd6(3) 163 md(9) 205 rxd8(0) 38 txd1(3) 80 rxd4(0) 122 vdd 164 md(8) 206 rxd8(1) 39 vss 81 rxd4(1) 123 rxer7 165 vss 207 rxd8(2) 40 rxer2 82 rxd4(2) 124 rxdv7 166 md(7) 208 rxd8(3) 41 rxdv2 83 rxd4(3) 125 col7 167 md(6) 42 col2 84 txclk1 126 crs7 168 md(5)
DM8108 8 port 10/100m fast ethernet switching controller preliminary 7 version: DM8108-ds-p02 november 25, 1999 pin description (continued) please refer to the ?strap pin default value after r eset section ? for the detail description of the strap pins. dram interface pin no. pin name i/o description 139 ? 146, 148 ? 155, 157 ? 164, 166 ? 173 md(31:0) i/o dram data lines 31 ? 0 183 ? 184, 186 ? 189, 191 ? 195 ma(10:0) i/o dram address lines 10-0; strap pins during reset ma9: 0= enable limit4, 1=disbale limit 4 ma8: dram size selection; 0= 1m, 1=2m ma7-0: auto-negotiation enable for port 7-0; 0= enabled 177 sras* o row address strobe for sdram 178 sdcas* o column address strobe for sdram 180 sdwe* o write cycle indication, internally pulled up 182 sdqm o data mask for sdram 179 sdcs* o chip select for sdram expansion bus pin no. pin name i/o description 204 rxdvclk i/o expansion port?s receiving data valid 208 ? 205 rxd8[3:0] i/o expansion port?s receive data i nput 197 txenclk i/o expansion port?s transmit enable output 202 ? 199 txd8[3:0] i/o expansion port?s transmit data output strap pins during reset: txd8[2:0] = device # setting txd8[3] = dram timing led interface pin no. pin name i/o description 2 ledclk o led data clock 4 ledd o led data: active low. data stream that contains led indicators per port. the data is shifted out and should be qualified by lds tb* to clock into external registers to drive leds. strap pin during reset: 0: expansion port with f ast speed 1: expansion port with lower apees 3 ldstb i/o led data strobe: active high. used to strobe the ld into an ext ernal register strap pin during reset: 0: force link 1: link detection through serial mii
DM8108 8 port 10/100m fast ethernet switching controller 8 preliminary version: DM8108-ds-p02 november 25, 1999 mii interface pin no. pin name i/o description 133,117,101, 85,66,50,34,18 txen(7:0) b transmit enable: active high, synchr onous to txclk; indicate that the transmission data is valid. strap function during reset-- txen(7:0): 0 = port 7-0 full duplex 132,116,100,84, 65,49,33,17 txclk(7:0) i transmit clock: provides the timing reference for the transfer of txen, txd signals. it is 25mhz for 100mbps and 2.5mhz for 10mbps. 22 ? 19 txd0(3:0) b transmit data for port 0; synchronous to txclk0. strap function during reset-- tdx0[0]: 0=80mhz, 1=66mhz clock operation txd0[1]: 0=enable par tition mode, 1=disable partition mode txd0[2]: 0=enable ex pansion port, 1=disable ex pansion port txd0[3]: 0=init only, 1= enable bist 38 ? 36 txd1(3:0) b transmit data for port 1; synchronous to txclk1. strap function during reset -- txd1[2:0]: test mode txd1[3]: 0=enable crc, 1=disbale crc 54 ? 51 txd2(3:0) b transmit data for port 2; synchronous to txclk2. strap function during reset -- txd2[2:0]: device # setting txd2[3]: dram timing 0=fast, 1=slow 70 ? 67 txd3(3:0) b transmit data for port 3; synchronous to txclk3. strap function during reset -- txd3[0]: 0=max. packet size 1536, 1=max. packet size 1518(default) txd3[1]: 0=enable back_pressure, 1= disable (default) txd3[3:2]: age strap pins 00= 64 sec. 01= 128 sec. 10= 256 sec. 11= disbale 89 ? 86 txd4(3:0) o transmit data for port 4; synchronous to txclk4. strap function during reset ? txd4[0]: 0= port 0 trunking enable 1= port 0 no trunking (default) txd4[1]: 0= port 1 trunking enable 1= port 1 no trunking (default) txd4[2]: 0= port 2 trunking enable 1= port 2 no trunking (default) txd4[3]: 0= port 3 trunking enable 1= port 3 no trunking (default) 105 ?102 txd5(3:0) o transmit data for port 5; synchronous to txclk5. strap function during reset ? txd5[1:0]: broadcast filtering rate selection 00 = 8k/sec 01 = 16k/sec 10 = 64k/sec 11= disable 121 ?118 txd6(3:0) o transmit data for port 6; synchronous to txclk6. 137 ?134 txd7(3:0) o transmit data for port 7; synchronous to txclk7. 16 ? 13 rxd0(3:0) i receive data for port 0; synchr onous to rx clk0. 32 ? 29 rxd1(3:0) i receive data for port 1; synchr onous to rx clk1. 48 ? 45 rxd2(3:0) i receive data for port 2; synchr onous to rx clk2. 64 ? 61 rxd3(3:0) i receive data for port 3; synchr onous to rx clk3. 83 ? 80 rxd4(3:0) i receive data for port 4; synchr onous to rx clk4.
DM8108 8 port 10/100m fast ethernet switching controller preliminary 9 version: DM8108-ds-p02 november 25, 1999 99 ? 96 rxd5(3:0) i receive data for port 5; synchr onous to rx clk5. 115 - 112 rxd6(3:0) i receive data for port 6; synchr onous to rx clk6. 137 - 128 rxd7(3:0) i receive data for port 7; synchr onous to rx clk7. 127,111,95,79, 60,44,28,12 rxclk(7:0) i receive clock for port 7 ? 0; synchronous to rxd, rxdv,rxer; has same clock rate as txclk. 124,108,92,76, 57,41,25,9 rxdv(7:0) i receive data v alid indicat ion for port 7 ? 0. 123,107,91,75, 56,40,24,8 rxer(7:0) i receive data error indication for port 7 ? 0. 126,110,94,78, 59,43,27,11 crs(7:0) i carrier sense; active high. indicates that either the transmit or receive medium is not idle. crs is not synchronous to any clock. 125,109,93,77, 58,42,26,10 col(7:0) i collision detect; active high. indicates a c ollis ion has been detected on the wire. this input is ignored during full duplex operation and in the half duplex mode while txen of the same port is low. 72 mdclk i/o serial mii management interface clock signal: 1mhz clock for mdio data reference. connected to all phy po rts; it is an input pin if the device # is not 0 in sdram mode; else, it is an output pin. 73 mdio i/o serial mii management interface data; this bi-direc tion line is used to transfer control information and s tatus between the phy and the DM8108. it conforms to the ieee-802.3 specifications. this signal may be connected to the phy devices of all ports. pulled down if not used. miscellaneous interface pins pin no. pin name i/o description 175 sclk i memory clock: used by the dram state machine. 5 rst* i reset signal for the chip. 6 testen* i test pin to enable test functions power pins pin no. pin name i/o description 23,55,90,122, 156,185,198 vcc power connected to 3.3v power plane 1,7,39,71,74, 106,138,147, 165,174,176, 181,190,196, 203 gnd ground connected to ground plane
DM8108 8 port 10/100m fast ethernet switching controller 10 preliminary version: DM8108-ds-p02 november 25, 1999 o ptional functional description fast ethernet ports functional overview the DM8108 is a high-performance, low-cost fast ethernet switching controller which provides packet switching between eight on-chip, 10/100 mbps ports and one optional expansion port. it is suitable for the auto-sensing 10/100mbps switch appli cation. switching architecture the switching architecture is based on the shared memory and handshaking signals to switch packets betw een on-chip ports hard-wired. for an incoming packet, the receiving port?s mac stores it in the receiving buffers if it is a good packet. at the same time, the switching engine determines which port the pa cket will forward to and update the address table which w ill be used for future packet forwarding reference. fast ethernet ports the DM8108 integrates eight fast ethernet ports, working at 10/100mbps (half-duplex) or 20/200mbps (full-duplex) with off-the-shelf phy chips. the interface is glue-less through media independent interfaces (mii). the auto- negotiation function determines the port?s operating mode. with auto- negotiation disabled, the ports can be forced to operate at a certain m ode, if so desir ed. each port incl udes the media access control function (mac), led signals for link, collision, receive/transmit, half/full duplex and receive buffer full indications. address rec ognition the DM8108 in a system can rec ognize up to 16k uni-cast mac addresses and unlimi ted m ulticast/b roadcast mac addresses. an inte lligent address recognition mechanism enables filtering and forwarding packets at full ethernet wire speed. the DM8108 provides an address self-learning mechanism. as each DM8108 learns new address, it updates the address table in the stor age. fig.1: typical 10/100 mbps auto-sensing swit ching hub application switch ports switch ports DM8108 10/100 mbps phy m em mem DM8108 10/100 mbps phy
DM8108 8 port 10/100m fast ethernet switching controller preliminary 11 version: DM8108-ds-p02 november 25, 1999 packet routing as any port in the DM8108 receives a packet, the DM8108 will put the received data in the rec eiving buffer and start the address recognition at same time. 1. if the destination address is pointed to a local port other than receiving port, the dm 8108 w ill update the transmit descriptor of the target port with the buffer location and byte count information and wait for transmission. 2. if the destination address is pointed to a port loca ted in other devices, the DM8108 w ill update the transmit descriptor of the expansion port with the receiving buffer location and byte count information and wait for transmission. 3. i f the destination address is not found in the address table, the DM8108 w ill update all the transmit descriptors, except the one of the receiving port, for transmission. 4. for the multicast/broadcast addresses, the DM8108 simply updates all the transmit descriptors, except the one of the receiving port or the ports that are disabled, for transmission. 5. for bad packet, the dm 8108 simply dis cards it. 6. if the receiving buffer or the transmit descriptor for a particular port is full, the packet will be lost. network management features the DM8108 is targeted for the non-managed ethernet switching application. no management functions provi ded. dram interface the DM8108 interfaces to 1m or 2m bytes of sgram or sdram. the dram is used to store incoming packets as well as he address table and transmit descriptors. the dram can operate at up to 90mhz. one 256kx32 or 512kx16 sgram are required respectively for 1m or 2m shared memory size. expansion bus the expansion bus contains receive port and transmit port. each port is 4-bit wide. the receive port takes the incoming packet into a fifo that has to be distributed to the receiving buffer immediately. at the same time, the DM8108 w ill check the destination and source addresses to determine the target port and update the address t able if necessary. the transmit port is dedicated for transferring packets out to other switching members if the transmit descriptor for this port saying the transmission is pending. total of 8-DM8108 can be cascaded for a 64-port switching system.
DM8108 8 port 10/100m fast ethernet switching controller 12 preliminary version: DM8108-ds-p02 november 25, 1999 operation overview the sw architecture family of switching devices has been defi ned as low cost, high perform ance and scalable architecture for a small switching system of packetized data. var ious devices will be developed. the oems will be able to design r obust switching configurations based on the sw architecture. the sw architecture family uses a ?store-and- forward? switching approach. this approach has the following advant ages: ? store-and-forward switches allow switching between differing speed media (e.g. 10mbps and 100mbps). ? store-and-forward switches improve overall network performance by acting as a ?network cache?, effectively buffering packets during times of heavy c ongestion. ? store-and-forward switches prevent the erroneous packets from forwarding by analyzing the frame check sequence (fcs) before forwarding to the destination port. ? store-and-forward switches prevent illegal frames (runt or oversized) from being forwarded and thereby reduce the congestion caused by bad pack ets. the basic operation of dm 8108 is very simple. the DM8108 receives the incoming packets from the ethernet ports, searches in the address table for the destination mac address, and forwards the packet to the appropriate port, which could be either local (one of the DM8108?s port) or in a different DM8108 device that resides on the expansion bus. if the destination addr ess is not found, the packet will be treated as a multicast packet and sent to every port (other than the source port) and other devices on the expansion bus. the DM8108 automatic ally learns the port number of attached network devices by examining the source mac address of all incoming packets. if the source address is not found in the address table, the device adds it to the table (with source port and device information). the address table is managed by DM8108 individually. address learning the DM8108 can learn up to 16k unique mac addresses. addresses are stored in the address table located in the dram which will be initialized after reset. packet buffering incoming packets are buffered in the dram array. these buffers provide elastic storage for transferring data between low-speed and high speed segments. the packet buffers are managed automatically by the dm 8108. packet forwarding protocol the DM8108 updates the transmit descriptor of the target port, which is learned from address table, with the received packet buffer location and pa cket l ength. the mac of target port will fetch the packet for trans miss ion once the memory bus is available. expansion bus the expansion bus is defined as a spe cial case of a normal fast ethernet mii port except running at much higher data rate. the designer can link several dm 8108s wi thin a switching box or can link several switching boxes.
DM8108 8 port 10/100m fast ethernet switching controller preliminary 13 version: DM8108-ds-p02 november 25, 1999 theory of operation block diagram e xpansion control registers status registers mac dram controller led control u nit switching engine mac mii management
DM8108 8 port 10/100m fast ethernet switching controller 14 preliminary version: DM8108-ds-p02 november 25, 1999 media access control the mac engine incorporates the essential protocol requirement for an ethernet ieee-802.3 compliant node, and provides the interface betw een the fifo subsystem and the m ii. the mac has two primary attributes: transmit and receive message data encapsulation the mac will discard the ill egally short (less than 64 bytes of frame data) or oversized (greater than 1536 bytes) messages to be transmitted or received. framing (frame boundary delimitation, f rame synchronization) the mac engine w ill automatically handle the construction of the transmit f rame. once the transmit fifo has been f illed to the predetermined threshold and access of the channel is permitted, the mac will commence the following for transmission: the receiving section of the mac will detect an incoming preamble sequence when the rxdv signal is activated by the external phy. the mac will discard the preamble and begin searching for the sfd. once the sfd is detected, all the subsequent nibbles are treated as part of the frame. the mac will dis card the message if it is shorter than 64-bytes or longer than 1518 (1536) bytes. the received frame will be sent to receiving buffer for switching. if the frame terminates or suffers a collision before 64-bytes (after sfd) have been received, the mac will automatically delete the frame from fifo. addressing (source and des tination address handling) the mac intercepts the source and des tination address from the incoming frame and send them to switching engine for the following purposes: . to update the address table . to learn the switching target . to detect the DM8108 predefined address for the device control functions. error detection (physical medium transmission errors) during transmission, if the switching engine failed to keep the transmit fifo f illed sufficiently, cause an underflow, the mac engine will guarantee the message is either sent as runt packet (which will be detected by the receiving station) or as an invalid fcs (which will cause the receiver to reject the pack et). during reception, the fcs is generated on every nibble (including the dribbling bits) coming from the cable, although the internally saved fcs value is only updated on the eighth bit (on each byte boundary). the mac engine will ignore up to 7 additi onal bits at the end of a message (dribbling bits), that can occur under normal network operating conditions. preamble 1010?1010 sfd 10101011 destination address source address length data fcs 7 bytes 1 bytes 6 bytes 6 bytes 2 bytes 40 ? 1500 bytes 4 bytes
DM8108 8 port 10/100m fast ethernet switching controller preliminary 15 version: DM8108-ds-p02 november 25, 1999 media access management ieee 802.3 protocols define a media access mechanism that permits all stations to access the channel with equality. any node can attempt to connect for the channel by waiting a predefined period of time (inter packet gap) after the last ac tivity before transmitting on the media. if two nodes simultaneously contend for the c hannel, their signals will interact causing loss of data, defi ned as co llision. it is the responsib ility of the mac to attempt to avoid and recover from the end-to- end transmiss ion to the receiving station. medium allocation (collision avoidance, except in full-duplex operation) the mac will monitor the medium for traffic by watching for carrier activity. when the carrier is detected, the media is considered as busy, and the mac should defer to the existing message. the mac implements the ieee-802.3 defi ned two part deferral algorithm, with inter-frame-spacng- part1 (ifs1) time for 64-bit time (6.4 us for10-base and 640 ns for 100-base). the inter-frame- spacing-part2 (ifs2) interval is, therefore, 32-bit time. the inter packet gap (ipg) timer will start timing the 96-bit time inter-frame-spacing after the rec eiving carrier is de-asserted. during the ifs1, the mac will defer any pending transmit frame and respond to the receive message. the ipg counter w ill be cleared to 0 continuously until the carrier de-asserts, at which point the ipg will resume the 96-bit time count again. once the ifs1 period has completed and the ifs2 has commenced, the mac will not defer to the receiving frame if a transmit frame pending. the mac will not attempt to receive the rec eiving f rame, since it will start transmit and generate a co llision at 96-bit time. the mac will complete the preamble (64-bit) and jam (32-bit) sequence before ceasing transmission and invoking the random back-off algorithm. contention resolution (collision handling, except in full-duplex mode) if a collision is detected thr ough col pin before the complete preamble/sfd sequence has been transmitted, the mac engine w ill complete the preamble/sfd before appending the jam sequence. if a collision is detected after the preamble/sfd has been completed, but prior to 512 bits being transmitted, the mac will abort the transmission and append the jam sequence immediately. the jam sequences is a 32-bit all ?34? pattern. the mac will attempt to transmit a f rame a total of 16 times (15-retries) due to normal c ollisions ( those within the slot time). detection of collision w ill cause the transmission to be re-scheduled to a time determined by the random back-off algorithm. if 16 attempts experienced collisions, the transmitting message w ill be flus hed from fifo. if a collision is detected af ter 512- bit ti mes have been transmitted, the collision is termed ?late? collision. the mac will abort the transmiss ion, append the jam sequence. no retry attempt w ill be sc heduled on detection of late c ollision, and transmit mess age will be flushed from the fifo. the mac implements the truncated exponential back-off algorithm defined by the 802.3 standard. in full-duplex mode, the mac transmits unconditionally.
DM8108 8 port 10/100m fast ethernet switching controller 16 preliminary version: DM8108-ds-p02 november 25, 1999 10/100 mbps mii half? duplex transmission when the mac has a frame ready for transmission, it samples the link activity. if the crs signal is inacive (no activity on the link), and the ipg counter has expired, frame transmission begins. the data is transmitted through txd(3:0) of the transmitting port, clocked on the rising edge of txclk. the txen is asserted at same time. in case of co llision, the phy asserts the col signal on the mac, which w ill then stop the transmission and w ill perform c ontention resolution. the retry policy is based on the: transmit exception conditions under normal operating conditions the mac will ensure that the collisions that occurred within 512 bit times from the start of transmission (including preamble) to be automatically retried with no switching engine intervention. the transmit fifo ensures this by guaranteeing that the data contai ned wi thin the fifo will not be ov erwritten until at least 64 bytes (512 bits) of preamble plus address, length, and data fields have been transmitted onto the network without encountering a c ollis ion. in full- duplex mode, the data in the fifo can be overwritten as soon as it is transmitted. under abnormal operating conditions . late collision the mac will abandon the transmit process for that frame, and process the next transmit frame in the ring. frame experiencing a late co llision will not be retried. txclk txen, txd(3:0) 0ns ? 25ns 10/100 mbps mii half- duplex r eception frame reception starts with the assertion of rxdv (while the mac is not transmitting) by the phy. once rxdv is asserted, the mac will begin sampling the incoming data on pins rxd(3:0) on the rising edge of rxclk. reception ends when the rxdv is de- asserted by the phy. the last nibble sampled by the mac is the nibble present on rxd(3:0) on the last rxclk rising edge in which rxdv is still asse rted. if mac detected the assertion of rxer while rxdv is asserted, it will desi gnate this packet as corrupted. the following figure shows the mii receive signals timing. 10ns min. rxclk rxdv, rxer, rxd(3:0) 10ns min.
DM8108 8 port 10/100m fast ethernet switching controller preliminary 17 version: DM8108-ds-p02 november 25, 1999 receive exceptional conditions normal network operating conditions during the reception, the mac will ensure that if collision occurs during packet re ception, the packet will be automatically deleted from the receive fifo. the receive fifo also will delete any frame that is composed of fewer than 64 bytes (runt packet). abnormal network operating conditions abnormal network c onditions include: . fcs errors reception and checking of the received fcs is performed automatically by the mac. the equation is: 32 26 23 22 16 12 11 10 8 7 5 4 2 1 x + x + x + x + x + x + x + x + x + x + x + x + x + x + 1 if any fcs error occurred, the mac will discard the packet. . late collision late collision is the collision being detected after 512-bit times while receiving. . fifo transfer error the mac also monitors fifo overflow status, which will force the most recent receiving packet (not finished) in the fifo be discar ded. back-pressure the DM8108 w ill generate ?jam pattern? to force collision on the media as far as it finds out that the internal resources can not meet it demands. 10/100 mbps full-duplex operation when operating in the full-duplex mode, the crs signal is associated with the received frames only and has no effect on the transmitted f rames. the col signal is ignored by the mac while in full- duplex mode. transmission starts when txen goes active; regardless the state of rxdv. reception starts when the rxdv signal is asserted indicating traffic on the receiving port. the DM8108 suppo rts i eee 802.3x pause function in the full duplex mode operation. during receiving, the DM8108 w ill issues pause command with the largest timer value to stop the transmitter if the receiving buffer pointer is above the full threshold value (high water mark). when the receiving buffer pointer is below the not-f ull threshold value (low water mark), it will i ssue another pause command with zero timer value to start the transmitter. the DM8108 is able to monitor the pause command and stop transmitting accor dingly to the timer value specified in the command packet.
DM8108 8 port 10/100m fast ethernet switching controller 18 preliminary version: DM8108-ds-p02 november 25, 1999 functional blo cks of the mac transfer control l ogic transfer counters tx fifo rx fifo command & status r egisters protocol pla fifo control l ogic address recognition l ogic receive control l ogic collision, recovery & i pg timing crc generator c hecker transmit control l ogic m u x m u x preamble/synch jam pattern gen.
DM8108 8 port 10/100m fast ethernet switching controller preliminary 19 version: DM8108-ds-p02 november 25, 1999 mii management mii management registers serial access the mii specification defines a set of 32 16- bit status and control registers that are addressable through the serial data interface pins mdclk and mdio. please refer to a phy device?s spec for the definition of the registers. the DM8108 w ill initialize mii management registers accessing after reset. in edo memory configuration mode, the DM8108 acts as serial mii initiator. in sdram memory configuration, only the DM8108 whose device # equals to 0 is the initiator. other devices cascaded w ill be the list ener to extract the auto- negotiat ion information from mid stream. mdclk has a maximum clock rate of 2.5mhz. the mdio line is bi-directional and may be shared by up to 32 devices. the protocol and the access waveform are shown below: mdclk z z mdio (DM8108) z z mdio (phy) z 0 1 1 0 0 1 1 0 0 0 0 0 0 0 z 0 0 0 1 1 0 0 0 1 0 0 0 0 0 0 0 0 z adle start op code phy address register address tr register data figure typical mdio read operation mdclk mdio z (DM8108) z 0 1 0 1 0 1 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 z idle start op code phy address register address tr write data figure typical mdio write operation protocol < data > read operation < z >< 01 >< 10 >< xxxxx >< xxxxx >< z0 > write operation < z >< 01 >< 01 >< xxxxx >< xxxxx >< 10 > table mii management serial protocol
DM8108 8 port 10/100m fast ethernet switching controller 20 preliminary version: DM8108-ds-p02 november 25, 1999 auto-negotiation auto-negotiation disabled when aneg* (ma[7:0]) strap pin is high, auto- negotiation is disabled, and the corresponding port can be selected as half- or full- duplex mode respectively. following the reset the port duplex mode is set by the state sampled on the txen(7:0) pins. the speed that each port operates in (10mbps or 100mbps) is determined by the frequency of txclk(7:0) and rxclk(7:0) generated by phy. the phy generates 25mhz clock for both txclk and rxclk in 100mbps operation and 2.5mhz clock in 10mbps operation. auto-negotiation enabled when aneg* (ma[7:0]) pins are tied low, the mac decodes the duplex m ode from the values of the auto-negotiation advertisement register and the auto-negotiation link partner ab ility register at the end of auto- negotiat ion process. once the duplex mode is resolved, the DM8108 updates the port control registers. the DM8108 w ill conti nuously perform the following operations for each port (phy address 0-7 alternatively), implemented as read commands issued via the mdclk/mdio interface: link detection and link detection bypass (flnk*) the DM8108 w ill conti nuously query the phy devices for their link status associated with auto-negotiation process. the DM8108 w ill alternatively read registers from phy address 0 to 7 and update the internal link bits according to the value of bit 2 of register 1. in case of link down (bit 1.2=0), that port will enter ?link test f ail state?. in this state, all the port?s logic go to a reset state. the port will enter the ?link up state? if the bit 1.2 is ?1? or the flnk* (force link, ledstb* strobed low during reset) pin is sampled low during reset. partition mode a port enters partition mode when more than 64 consecutive collisions are s een on the port. in partition mode the port conti nuous to transmit but it w ill not receive. a port returned to normal operation mode w hen a good packet is seen on the wire. enabling partition mode partitioned mode is enabled always. entering partition state a port will enter the partition state w hen paen* strap pin sampled low during reset and when either of the following conditions occurs: the port detects a c ollis ion on every one of 64 consecutive re-transmit attempts to the same packet. the port detects a single c ollis ion which occurs for more than 512 bit times. while in partition state: the port will continue to transmit its pending packet, regardless of the co llision detection, and w ill not allow the usual back-off algorithm. addit ional packets pending for transmission, w ill be transmitted, while ignoring the internal co llision indication. this frees up the port?s transmit buffers which would otherwise be filled up at the expense of o ther ports buffers. the assumption is that the partition is signifying a system failure situation (bad connection/cable/station), thus dropping packets is a small price to pay vs. the cost of halting the switch due to a buffer full condition. the partition indication is available via the led interface. exiting from partition state the port exits from partition state, following the end of a successful packet transmission. a successful packet transmission is defined as no c ollisions were detected on the first 512 bits of the transmission. expansion bus the expans ion bus operates at full-duplex mode that provides up-to 7200mbps bandw idth for device to device connection. several DM8108 can be cascaded as a pipe to provide a robust ethernet switching system. the bus itself is very si mple. the transmit and receive ports contain independent data, valid and handshake si gnals. no bus arbitra tion is involved.
DM8108 8 port 10/100m fast ethernet switching controller preliminary 21 version: DM8108-ds-p02 november 25, 1999 the receive port utilizes the rdvclk to clock in the received data into fifo and uses rxtog r equests for a receiving buffer block. the switching engine will execute the similar process as for the ethernet ports. the transmit port appends the sync. field to a normal ethernet packet and sends the packet out thr ough td (3:0) at the rising edge of tx enclk. txenclk td(3:0) nib n-1 nib n nib n+1 switching engine all the packet switc hing is processed by the switching engine, which has following functions: mac address learning process the DM8108 has a self-learning mec hanism for learning the mac addresses of attached fast ethernet devices in real time. the DM8108 searches for the source address of an incoming packet in the address table and acts as follows: if the source address was not found in the address table, the DM8108 waits until the end of the packet (no e rror) and updates the address table. if the source address was found in the address table, the DM8108 waits for a good packet re ceived i ndication. address rec ognition the DM8108 forwards the incoming pack ets to appropriate port(s) according to the destination address as follows: if the packet is from a local port-- 1) if it is a unicast address and the addr ess is found in the address table, the DM8108 w ill: . if the port number recor ded is matc hed to port number on which the packet received, the packet is discarded. . if the port numbers are different, the packet is forwarded to the appropriate port. 2) if it is a unicast address and the addr ess is not found in the address table, the DM8108 acts as if the packet is a m ulticast packet and forwards it to the expansion transmit port and all the local ports except the incoming port, 3) if it is a multicast/broadcast address, the packet is forwarded to the expansion transmit port and all local ports (except to the port on which the packet was received). if the packet is from ex pans ion bus? 1) if it is a unicast address specified in the destination address in the ethernet packet, the DM8108 w ill: . if the recorded port pointed to a local port, the packet will be forwar ded to that port. . if the destination address is not found (not recorded by the mac address learning process), the packet will be forwarded to all the local ports and the expansion transmit port. 2) if it is a multicast/broadcast address (destination device # should set invalid), the packet w ill be forwarded to all the local ports and the ex pansion transmit port. address aging the DM8108 includes hardware to support for automatic address aging. buffers and q ueues the DM8108 incorporates 3 transmit queues and one common receive buffer area for the two fast e thernet ports and the expansion port, the queues and buffers are located in the dram along with address table. the
DM8108 8 port 10/100m fast ethernet switching controller 22 preliminary version: DM8108-ds-p02 november 25, 1999 DM8108 data structure com ponents are the following: receiving buffer ? a common receive buffer is allocated for each fast ethernet receiving port and expansion bus receiving port. the size of the receiving buffer is defined as 642kb (448 blocks) or 1728kb (1152 blocks) (depending on the dram size) of 1.5k bytes each. the DM8108 allocates the buffers to the 8 ethernet ports and the ex pansion port. transmit descriptors (txdr) ? a set of 9 transmit descriptor rings. each ring contains 512 descriptors. the descriptor?s size is 32-bit and contains the receiving buffer?s block number, the packet length and the packet type (m ulticast or uni-cast). the transmit descriptors reside in the dram. read/write pointers ? 9 pairs of pointers to the transmit descriptors. 23 22 1211 0 empty list tx descriptors: 1k x 3 receive buffer frame # 0 frame # 1 frame # 2 frame # n m/ -u byte count block number r ead pointer write pointer next empty rx block #
DM8108 8 port 10/100m fast ethernet switching controller preliminary 23 version: DM8108-ds-p02 november 25, 1999 DM8108 dram address mapping memory size queue & buffers description 1m byte 2m byte receive buffer 864kb ( 576 bl ocks) 1872kb (1248blocks) + unused 028000 ? 0fffff 028000 ? 1fffff acc count 8kb 026000 ? 027fff 027000 ? 027fff reserved 4kb 025000 ? 025fff 025000 ? 025fff tdr queue 20kb 020000 ? 024fff 020000 ? 024fff address table 128kb 000000 ? 01ffff 000000 ? 01ffff address table the address table structure occupies 128k bytes of memory and is controlled and initia lized by the DM8108. following reset, the DM8108 initializes the address table by invalidating the valid bit of all entries. field description v valid ? indicates a valid entry; 0 ? not valid, 1 ? valid. address (47:0) source mac address. unicast address only port # port number ? indicates which of the 3-port in a DM8108 is associated with this source address. 0h ? 1h: port 0 ?port 1 (2 ethernet ports); 2h: expansion port. reserved device # device number?indicate which device in the switching system is associated with this source address time stamp 4-bit tag?used to identify the update sequence. if the entry-block(4-entry) pointed by a mac address i ndex are all occupied, the entry that has oldest time stamp will be replaced. packet forwarding the following sections describe the procedures for forwarding packets under different s ituations: forwarding a uni-cast packet to a local ethernet port the incoming packet is fed to the rx fifo and is transferred to an empty block in the receive buffer area of dram. the switching eng ine will claim the block by setting the empty list not empty. in case of collision or fifo overflow, trans fer error etc . , the engine has to reset the empty list associated with the block. in parallel, an address rec ogni tion cycle will be performed for both the destination and source address. the DM8108 w ill use sa to learn a new or changed address entry. the da w ill point to an entry that specifies the local port?s number. at the end of reception of an error-free packet, the packet information is written to the appropriate port?s transmit descriptor. this information includes the byte count, receive block address which points to the write pointer, and the priority indication. the write pointer of the outgoing port?s transmit descriptor is incremented. the target port prepare for transmission whenever the write pointer and the read pointer are not equal. the engine resolves the priority issue and f ills the tx fifo before starting the transmission. if any tx fifo under run s ituation happens, the mac has to force the packet ?bad? and inform the engine to retry. at the end of the good transmit process, the target port increments the read pointer. the engine clears the appropriate bit in the empty list.
DM8108 8 port 10/100m fast ethernet switching controller 24 preliminary version: DM8108-ds-p02 november 25, 1999 forward a multicast, broadcast and ?unknown? packet if the received packet?s da is not found in the address table, or the packet is a multicast or broadcast packet, it will be treated as a multicast packet, the switching engine w ill perform most of the steps ment ioned above and forwards the packet to all ports. dram controller the DM8108 includes direct support for synchronous dram. the dram interface is entirely glue-less. all the accesses are performed as 32-bit. the memory controller is designed targeting up to 90-mhz. the DM8108 refreshes the dram automatically. following the reset, the dram controller will perform dram testing by write/ read several patterns and invalidate all the ent ries in the address table. the dram test result is sent out through the led status outputs. led interface the DM8108 provides led data bus, address bus and strobe signals to: display the chip or ports? configuration and transfer status, display the critical state signals for debug purpose. led signals definition the following timing diagram shows the interface of led bus while displaying led si gnals. 1us ldclk ldstb ld for the led signals having dynamic characte ristics, the DM8108 will maintain the signal for a minimum of 4ms before sending to the led bus if the state is triggered. dynamic signal ld 4ms ? 8 ms
DM8108 8 port 10/100m fast ethernet switching controller preliminary 25 version: DM8108-ds-p02 november 25, 1999 the following table shows the multiplexed led signals. bit # signals bit # signals 1 primary_port status 0 (link 0) 41 transmit (4) 2 primary_port status 1 (link 1) 42 receiving (4) 3 primary_port status 2 (link 2) 43 co llision (4) 4 primary_port status 3 (link 3) 44 rx buffer full (4) 5 primary_port status 4 (link 4) 45 reserved 6 primary_port status 5 (link 5) 46 reserved 7 primary_port status 6 (link 6) 47 full duplex (4) 8 primary_port status 7 (link 7) 48 port speed (4) 9 transmit (0) 49 transmit (5) 10 receiving (0) 50 receiving (5) 11 collision (0) 51 collision (5) 12 rx buffer full (0) 52 rx buffer full (5) 13 reserved 53 reserved 14 reserved 54 reserved 15 full duplex (0) 55 full duplex (5) 16 port speed (0) 56 port speed (5) 17 transmit (1) 57 transmit (6) 18 receiving (1) 58 receiving (6) 19 collision (1) 59 collision (6) 20 rx buffer full (1) 60 rx buffer full (6) 21 reserved 61 reserved 22 reserved 62 reserved 23 full duplex (1) 63 full duplex (6) 24 port speed (1) 64 port speed (6) 25 transmit (2) 65 transmit (7) 26 receiving (2) 66 receiving (7) 27 collision (2) 67 collision (7) 28 rx buffer full (2) 68 rx buffer full (7) 29 reserved 69 reserved 30 reserved 70 reserved 31 full duplex (2) 71 full duplex (7) 32 port speed (2) 72 port speed (7) 33 transmit (3) 73 partition (0) 34 receiving (3) 74 partition (1) 35 collision (3) 75 partition (2) 36 rx buffer full (3) 76 partition (3) 37 reserved 77 partition (4) 38 reserved 78 partition (5) 39 full duplex (3) 79 partition (6) 40 port speed (3) 80 partition (7)
DM8108 8 port 10/100m fast ethernet switching controller 26 preliminary version: DM8108-ds-p02 november 25, 1999 81 runt packet (0) 105 link fail (0) 82 runt packet (1) 106 link fail (1) 83 runt packet (2) 107 link fail (2) 84 runt packet (3) 108 link fail (3) 85 runt packet (4) 109 link fail (4) 86 runt packet (5) 110 link fail (5) 87 runt packet (6) 111 link fail (6) 88 runt packet (7) 112 link fail (7) 89 jab packet (0) 113 pure_port_status(0) 90 jab packet (1) 114 pure_port_status(1) 91 jab packet (2) 115 pure_port_status(2) 92 jab packet (3) 116 pure_port_status(3) 93 jab packet (4) 117 pure_port_status(4) 94 jab packet (5) 118 pure_port_status(5) 95 jab packet (6) 119 pure_port_status(6) 96 jab packet (7) 120 pure_port_status(7) 97 under_flow(0) 121 dram test status 98 under_flow(1) 122 internal sram test status 99 under_flow(2) 123 expansion port rx buf. full 100 under_flow(3) 124 dynamic allocation buf. full 101 under_flow(4) 125-128 reserved 102 under_flow(5) 103 under_flow(6) 104 under_flow(7)
DM8108 8 port 10/100m fast ethernet switching controller preliminary 27 version: DM8108-ds-p02 november 25, 1999 strap pins during reset the following table shows the strap pins during r eset. symbol description ledstb strap pin during reset: 0= force link, 1= link detection through serial mii (default) ledd strap pin for txenclk frequency of ex pansion port: 0=fast, 1= slow (default) txd0[3:0] txd0[0]: strap pin for the operating fr equency 0=88mhz; 1= 66mhz (default) txd0[1]: strap pin to enable partition mode 0=enable; 1=disable (default) txd0[2]: strap pin to enable expansion port 0=enable; 1=disable (default) txd0[3]: strap pin to enable bist 0=init only; 1=enable (default) txd1[3:0] txd1[2:0]: test function txd1[3]: disable crc checking 0= disable; 1=enable (default) txd2[3:0] strap pins during reset: txd2[2:0] = device # setting txd2[3] strapped for dram timing: 0=fast, 1= normal (default) txd3[3:0] strap pin during reset: txd3[0] max packet size selection: 0 = 1536 bytes, 1=1518 bytes (default) txd3[1] back pressure and flow cont rol enable: 0 = enable, 1 = disable (default) txd3[3:2] aging timing selection: 00 ? 64sec. 01 ?12 8 sec. 10 ? 256 sec. 11 ? disable (default) txd4[3:0] strap pin during reset: txd4[0] port 0 trunking selection: 0 = enable, 1=disable (default) txd4[1] port 1 trunking selection: 0 = enable, 1=disable (default) txd4[2] port 2 trunking selection: 0 = enable, 1=disable (default) txd4[3] port 3 trunking selection: 0 = enable, 1=disable (default) txd5[1:0] strap pin during reset: txd5[1:0] broadcast filtering rate selection: 00 = 8k packets/sec. 01 = 16k packets/sec. 10 = 64k packets/sec. 11 = disable (default) txen(7:0) strap pins during reset for ports? operating mode: 0= full duplex, 1=half duplex (default) ma9 strap pin during reset: 0= limit4 enabled, 1= disabled (default) ma8 strap pin during reset for memory size selection: 0= 2mb, 1= 1mb (default) ma(7:0) strap pins during reset: ma7-0: auto-negotiation enable for po rt0: 0= enabled (default), 1 = disabled
DM8108 8 port 10/100m fast ethernet switching controller 28 preliminary version: DM8108-ds-p02 november 25, 1999 absolute maximum ratings absolute maximum ratings ( 25 c ) symbol parameter min. max. unit conditions vcc supply voltage -0.3 3.6 v vi input voltage -0.3 5.25 v vo output voltage -0.3 vcc + 0.3 v io output current 2 24 ma iik input protection diode current ma iok output protection diode current ma tc operating temperature 0 70 c tstg storage temperature -40 125 c esd static discharge voltage 2000 v operating conditions symbol parameter min. max. unit conditions vcc supply voltage 3.3 3.6 v vi input voltage 0 vcc v vo output voltage 0 vcc v tc operating temperature 0 70 c cin input capacitance pf cout output capacitance pf comments stresses above those listed under ?absolute maximum ratings? may cause permanent damage to the device. these are stress ratings only. functional operation of this device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability.
DM8108 8 port 10/100m fast ethernet switching controller preliminary 29 version: DM8108-ds-p02 november 25, 1999 dc electrical characteristics (0 c DM8108 8 port 10/100m fast ethernet switching controller 30 preliminary version: DM8108-ds-p02 november 25, 1999 sclk t3 min t3 min t3 max t3 max ac electrical characteristics & timing waveforms (tc = 0 ? 70 c; vcc = 3.3v 5%) symbol signals parameter min. max. unit conditions sclk system clock frequency 66 90 mhz sclk rise/fall time 1 4 ns rst* reset pulse width 2 sclk t3 ma, md, cas*, ras*,dwe*, sdqm, scs*,sras*, scas* delay from sclk rising or falling edge 28ns t4 md, rxd8 (1) setup time 2 ns t5 md, rxd8 (2) hold time 2 ns t6 md float delay 2 8 ns t7 md, txd8 (3) drive delay 2 8 ns notes: 1. md is related to sclk; rxd8 is related to rxdvclk. 2. md is related to sclk; txd8 is related to txenclk. 3. all delays, setup, and hold times are referred to sclk rising edge unless stated otherwise. 4. all outputs are specified for 25 pf load. 5. all inputs and outputs also refer to i/o si gnal behavior. output delay from rising edge
DM8108 8 port 10/100m fast ethernet switching controller preliminary 31 version: DM8108-ds-p02 november 25, 1999 sclk or txenclk t7 min t6 min t7 max t6 max sclk or rxdvclk t4 min t5 min setup and hold time from rising edge drive or float delay from rising edge
DM8108 8 port 10/100m fast ethernet switching controller 32 preliminary version: DM8108-ds-p02 november 25, 1999 package information qfp 208l outline dimensions unit: inches/mm 105 156 d h d b a a 2 a 1 h e e 208 157 1 52 f 104 d y g d see detail f seating plane l g d ~ ~ ~ l 1 c detail f g e 53 e symbol dimensions in inches dimensions in mm a 0.145 max. 3.68 max. a 1 0.004 min. 0.10 min. a 2 0.127 0.005 3.23 0.13 b 0.008 +0.002 0.20 +0.05 -0.002 -0.05 c 0.006 +0.004 0.15 +0.10 -0.002 -0.05 d 1.102 0.005 28.00 0.13 e 1.102 0.005 28.00 0.13 e 0.020 0.004 0.50 0.10 f 1.004 nom. 25.5 nom. g d 1.185 nom. 30.10 nom. g e 1.185 nom. 30.10 nom. h d 1.205 0.012 30.60 0.30 h e 1.205 0.012 30.60 0.30 l 0.019 0.008 0.50 0.20 l 1 0.051 0.008 1.30 0.20 y 0.004 max. 0.10 max. 0 ~ 10 0 ~ 10 notes: 1. dimensions d and e do not include resin fins. 2. dimensions f, g d, g e are for pc board surface mount pad pitch design reference only.
DM8108 8 port 10/100m fast ethernet switching controller preliminary 33 version: DM8108-ds-p02 november 25, 1999
DM8108 8 port 10/100m fast ethernet switching controller 34 preliminary version: DM8108-ds-p02 november 25, 1999 appendix: cascade three DM8108s to a 24-port switch illustration DM8108 DM8108 DM8108 dram rxd2 txd2 r xdvclk txenclk phy dram rxd2 txd2 r xdvclk txenclk phy dram rxd2 txd2 r xdvclk txenclk phy sgram sdram sdram
DM8108 8 port 10/100m fast ethernet switching controller preliminary 35 version: DM8108-ds-p02 november 25, 1999 ordering information part number pin count p ackage DM8108 208 qfp disclaimer the information appearing in this publication is believed to be accurate. integrated circuits sold by d avicom semiconductor are covered by the warranty and patent indemnification pro visions st ipulated in the terms of sale only. davicom makes no warranty, express, statutory, implied or by description regarding the information in this publication or regarding the information in this publication or regarding the freedom of the described chip(s) from patent infringement. further, davicom makes no warranty of merchantability or fitness for any purpose. davicom deserves the right to halt production or alter the spe cificat ions and prices at any time without notice. accordingly, the reader is cautioned to verify that the data s heets and other information in this publication are current before placing orders. pr oducts descri bed herein are intended for use in normal commer cial applications. applications involving unusual environmental or reliability requirements, e.g. m ilitary equipment or medical life support equipment, are specifically not recommended without additional processing by davicom for such applications. please note that application circuits illustrated in this document are for reference purposes only. davicom?s terms and conditions printed on the order acknowledgment govern all sales by davicom. davicom will not be bound by any terms inconsistent with these unless d avicom agrees otherwise in w riting. acceptance of the buyer?s orders shall be based on these terms. company overview davicom semiconductor, inc. develops and manufactures integrated circuits for integration into data communication products. our mission is to design and produce ic products that re the industry?s best value for data, audio, video, and interne t/intr anet applications. to achieve this goal, we have built an organization that is able to develop chipsets in response to the evolving technology requirements of our customers while st ill delivering pr oducts that meet their cost requirements. products we offer only produ cts that satisfy high performance requirements and which are compatible with major hardware and software standards. our currently available and soon to be released pr oducts are ba sed on our proprietary designs and deliver high quality, high performance chipsets that comply with modem communication standards and ethernet networking standards. contact windows for additional information about davicom pr oducts, contact the sales department at: headquarters hsin-chu office: 3f, no. 7-2, industry e. rd. ix, scienced-based industrial park, hsin-chu city, taiwan, r.o.c. tel: 886-3-579-8797 fax: 886-3-579-8858 taipei sales & marketing office: 8f, no. 3, lane 235, bao- chiao rd., hsin-tien city, taipei, taiwan, r.o.c. tel: 886-2-2915-3030 fax: 886-2-2915-7575 email: sales@davicom.com.tw warning conditions beyond those listed for the absolute maximum may destroy or damage the produ cts. in addition, conditions for sustai ned periods at near the limit s of the operating ranges will stress and may temporarily (and permanently) affect and damage structure, performance and/or function .

▲Up To Search▲

Price & Availability of DM8108

	To Download DM8108 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .